[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell/pch/acpi: Add PCIe register offsets

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46761 )

Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets
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soc/intel/broadwell/pch/acpi: Add PCIe register offsets

These are present in common southbridge ACPI code, and also exist on
Broadwell. Thus, add the definitions to align with common ACPI code.

Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761
Reviewed-by: Nico Huber 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/pch/acpi/pcie_port.asl
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl
index d48ecd0..988c817 100644
--- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl
+++ b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl
@@ -8,4 +8,10 @@
    Offset (0x4c),	// Link Capabilities
    , 24,
    RPPN, 8,	// Root Port Number
+	Offset (0x5A),
+	, 3,
+	PDC, 1,
+	Offset (0xDF),
+	, 6,
+	HPCS, 1,
 }