[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2

[Meera Ravindranath (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Meera Ravindranath.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59392

to look at the new patch set (#3).

Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2
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mb/intel/adlrvp: Enable CPU PCIe RP 2

Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath 
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59392/3