Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58316 )
Change subject: psp_verstage: convert relative address in EFS2 ......................................................................
psp_verstage: convert relative address in EFS2
Addresses in AMD fw table with EFS gen2 is relative address, but cezanne PSP doesn't accept relative addresses in update_psp_bios_dir().
Check for EFS gen2 and convert them as needed.
BUG=b:194263115 TEST=build and boot on guybrush and shuboz
Signed-off-by: Kangheui Won khwon@chromium.org Change-Id: I95813beba7278480e6640599fcf7445923259361 --- M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/include/soc/iomap.h 4 files changed, 15 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58316/1
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 236578b..23257ab 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -41,10 +41,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800
-#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */
+#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index be6b23d..1a8ecf1 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -43,6 +43,9 @@ #define MIN_TRANSFER_BUFFER_SIZE (8 * KiB) #define MIN_WORKBUF_TRANSFER_SIZE (MIN_TRANSFER_BUFFER_SIZE - TRANSFER_INFO_SIZE)
+#define EFS_GEN_MASK 1 +#define EFS_GEN2 0 + struct psp_ef_table { uint32_t signature; /* 0x55aa55aa */ uint32_t reserved0[4]; @@ -50,7 +53,7 @@ uint32_t bios0_entry; uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t reserved1; + uint32_t efs_gen; uint32_t bios3_entry; } __attribute__((packed, aligned(16)));
diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 7c37355..175d9c7 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -10,6 +10,7 @@ #include <console/console.h> #include <fmap.h> #include <pc80/mc146818rtc.h> +#include <soc/iomap.h> #include <soc/psp_transfer.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> @@ -121,6 +122,12 @@ return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; }
+ /* EFS2 uses relative address and PSP isn't happy with that */ + if ((ef_table->efs_gen & EFS_GEN_MASK) == EFS_GEN2) { + psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK); + bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK); + } + if (update_psp_bios_dir((void *)&psp_dir_addr, (void *)&bios_dir_addr)) { printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n"); return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index c56e7af..6dab976 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -66,10 +66,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800
-#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */
+#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */