[coreboot-gerrit] Change in ...coreboot[master]: PO changes 1. Fix PSF base address for CML PCH

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31434

Change subject: PO changes 1. Fix PSF base address for CML PCH
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PO changes 1. Fix PSF base address for CML PCH

Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/include/soc/pch.h
M src/soc/intel/cannonlake/lpc.c
3 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31434/1

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index f45e177..6c527e7 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -34,9 +34,11 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <soc/smbus.h>
+#include <string.h>

#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP	0x1400
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H	0x0980
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CMP_LP    0x0700

#define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
@@ -67,6 +69,8 @@
    	return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;
    else if (pch_series == PCH_LP)
    	return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;
+	else if (pch_series == PCH_CMP)
+		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CMP_LP;
    else
    	return 0;
 }
diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h
index 5253053..c3ce6ac 100644
--- a/src/soc/intel/cannonlake/include/soc/pch.h
+++ b/src/soc/intel/cannonlake/include/soc/pch.h
@@ -22,6 +22,7 @@

#define PCH_H				1
 #define PCH_LP				2
+#define PCH_CMP				3
 #define PCH_UNKNOWN_SERIES		0xFF

#define PCIE_CLK_NOTUSED		0xFF
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c33b3c3..6fc6c54 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -17,6 +17,7 @@

#include "chip.h"
 #include <delay.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <pc80/isa-dma.h>
@@ -77,10 +78,14 @@
     */
    lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);

+	printk(BIOS_DEBUG, "LPC DID: 0x%x", lpc_did_hi_byte);
+
    if (lpc_did_hi_byte == 0x9D)
    	return PCH_LP;
    else if (lpc_did_hi_byte == 0xA3)
    	return PCH_H;
+	else if (lpc_did_hi_byte == 0x02)
+		return PCH_CMP;
    else
    	return PCH_UNKNOWN_SERIES;
 }