[coreboot-gerrit] Change in coreboot[master]: lynxpoint/broadwell: Correct L1 exit latency with ASPM

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph.
Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/57501

to look at the new patch set (#3).

Change subject: lynxpoint/broadwell: Correct L1 exit latency with ASPM
......................................................................

lynxpoint/broadwell: Correct L1 exit latency with ASPM

Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).

Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/pch/pcie.c
M src/southbridge/intel/lynxpoint/pcie.c
2 files changed, 2 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/57501/3