Attention is currently required from: Marshall Dawson, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61461 )
Change subject: mb/amd/chausie: update GPIO for chausie ......................................................................
Patch Set 6:
(4 comments)
Patchset:
PS6: only had a brief look at this patch and haven't checked with the schematics
File src/mainboard/amd/chausie/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/61461/comment/af92e7a0_9bb478b9 PS6, Line 28: /* Deassert PCIe Reset lines */ i'd put this comment in the same level of indentation as the code
https://review.coreboot.org/c/coreboot/+/61461/comment/b6184867_4222784a PS6, Line 50: SMBUS0 this is the I2C2 SCL and not the SMBUS0 SCL, so the comment doesn't match the code. the smbus controller could also be muxed to those pins, but it isn't used here. same for the comments below
File src/mainboard/amd/chausie/gpio.c:
https://review.coreboot.org/c/coreboot/+/61461/comment/4d283c05_292e8ed9 PS6, Line 113: SMBUS0 see my comment on the other file