Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 )
Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/thermal.h:
https://review.coreboot.org/c/coreboot/+/59509/comment/2be4d0ec_782901d9 PS4, Line 20: #define GET_LTT_VALUE(x) ((x + 10) << 20 | (x + 5) << 10 | x)
Please wrap `x` in parentheses to avoid operation order problems: […]
Ack
File src/soc/intel/common/block/thermal/Kconfig:
https://review.coreboot.org/c/coreboot/+/59509/comment/2a81e1f3_f7bb1d71 PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH.
This is good idea to avoid user to select the both unknowingly for any platform.
Ack