Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43741 )
Change subject: WIP: A bunch of experiments for cr50 long pulses ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43741/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43741/2//COMMIT_MSG@15 PS2, Line 15: to FSP. For Volteer (and future Tigerlake boards) we enable mode S0i3.4
The very first proposal, was to add the functionality without adding one more point at which the AP […]
In my opinion, it is not too bad to have the extra call in ramstage to read cr50 version to determine if we want to enable low power state. Also, Volteer family would probably be one of the few (if not the only) to actually need this check. Adding all the extra logic to pass this very specific `tpm_board_cfg` does not seem worth the complexity.
Instead, what you are running into with the GSPI issue is an actual problem that needs to be addressed irrespective of how the solution is implemented here. I think it would be better to fix that problem which would let us have this check in those few boards which really need it.