Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58181 )
Change subject: soc/intel/common/cse: Support RW update when stitching CSE binary ......................................................................
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for including CSE RW update in CBFS. CSE_RW_FILE is set to either CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the selection of STITCH_ME_BIN config. Also, $(CSE_LITE_ME_RW)-file is updated to be evaluated every time it is used so that there is no dependency on the order of definitions in Makefile.inc.
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 11 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58181/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 247cc9f..5b3ad0b 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -64,7 +64,7 @@ CBFS name for Intel CSE CBFS RW version file
config SOC_INTEL_CSE_RW_FILE - string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE + string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN default "" help Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index fc54b82..4139b48 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -8,21 +8,24 @@
ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y)
-ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") -$(error "CSE RW file path is missing and need to be set by mainboard config") -endif - ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") $(error "CSE RW version is missing and need to be set by mainboard config") endif
-CSE_RW_FILE=$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +ifneq ($(CONFIG_STITCH_ME_BIN),y) + +ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") +$(error "CSE RW file path is missing and need to be set by mainboard config") +endif +CSE_RW_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) + +endif
CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \ $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME)) cbfs-files-y += $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE) +$(CSE_LITE_ME_RW)-file = $(CSE_RW_FILE) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw
@@ -53,6 +56,7 @@ CSE_BP1_BIN := $(objcse)/cse_bp1.bin CSE_BP2_BIN := $(objcse)/cse_bp2.bin CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin +CSE_RW_FILE := $(CSE_BP2_BIN)
CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION)) ifeq ($(CONFIG_CSE_BPDT_VERSION),)