[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Patrick Rudolph.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60789

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG
......................................................................

soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG

This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO
reset types in Alder Lake as below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- RSMRST for GPD/Reserved for GPP - (Value 11)

Hence, created two different reset types for `GPP` and `GPD`.
Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET().

BUG=b:213293047

Signed-off-by: Subrata Banik 
Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b
---
M src/soc/intel/alderlake/gpio.c
1 file changed, 23 insertions(+), 23 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/60789/2