[coreboot-gerrit] Change in coreboot[master]: soc/intel: Fix SMRAM base MSR

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34730 )

Change subject: soc/intel: Fix SMRAM base MSR
......................................................................

soc/intel: Fix SMRAM base MSR

Previous setting was correct but assumed SMI handler is
always located at the beginning of TSEG. Break the assumption.

Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730
Reviewed-by: Furquan Shaikh 
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/smmrelocate.c
3 files changed, 6 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index ef30078..4ae383e 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -192,10 +192,9 @@
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index dfdec22..11745b0 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -191,10 +191,9 @@
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index b69692f..42d15b7 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -201,10 +201,9 @@
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */