Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Meera Ravindranath, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60774 )
Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/60774/comment/ff2aed98_de8a0d18 PS4, Line 203: PWROK
Why not keep parity with the existing `PAD_CFG_NF()` macro and take the reset type as parameter?
@Angel, there is a design gap between GPIO PAD reset type and PAD lock configuration reset type. Hence, we wish to force PAD reset type in sync with lock reset type which is POWER GOOD. Please find detailed analysis below.
As per GPIO BWG, there are 4 types of GPIO reset types
Power Good (RSMRST# for GPP) - (Value 00) = Doesn't allow GPP reset except Deep Sx and G3. (Read as Sx state doesn't reset the GPP)
Deep (Value 01) = Almost same #1
Host Reset/PLTRST (Value 10) = Allow to reset the GPP in warm, Sx state etc.
RSMRST for GPD/Reserved for GPP
Now the Pad Config Lock for a GPP allows locking specific register fields in the PAD configuration register. The Pad Config Lock registers reset type is default hardcoded to #1 Power Good as per EDS) and it's "not" configurable by DW0.PadRstCfg. It may appear that for a GPP, the Pad Reset Config (DW0 Bit 31) is configured differently from #1 Power Good. This would create confusion where the Pad configuration is returned to its default value and its still lock, this would prevent SW to reprogram the GPP.
Hence, it's recommended to change the Pad Reset Config for lock GPP as #1 Power Good so that pad configuration and lock bit can be reset at the same time.