[coreboot-gerrit] Change in coreboot[master]: [WIP] AGESA fam14: Set Ontario link data

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37755 )

Change subject: [WIP] AGESA fam14: Set Ontario link data
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[WIP] AGESA fam14: Set Ontario link data

Change-Id: Ibc4f22d2f9396fdededa3f329015194c826bd8e9
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/amd/agesa/family14/fixme.c
M src/drivers/amd/agesa/bootblock.c
2 files changed, 17 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37755/1

diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 2b412fa..c9d3039 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -18,10 +18,6 @@
 #include <AGESA.h>
 #include <amdlib.h>

-/* Define AMD Ontario APPU SSID/SVID */
-#define AMD_APU_SVID		0x1022
-#define AMD_APU_SSID		0x1234
-
 void amd_initcpuio(void)
 {
    UINT64 MsrReg;
@@ -68,8 +64,6 @@
 void amd_initmmio(void)
 {
    UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
    AMD_CONFIG_PARAMS StdHeader;

/*
@@ -79,14 +73,6 @@
    MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
    LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);

-	/* Set Ontario Link Data */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
-	PciData = 0x01308002;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
-	PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
    /* Set ROM cache onto WP to decrease post time */
    MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
    LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c
index f45c9ab..9c8bea5 100644
--- a/src/drivers/amd/agesa/bootblock.c
+++ b/src/drivers/amd/agesa/bootblock.c
@@ -36,6 +36,23 @@
    MsrReg = 0;
    LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader);
 }
+
+
+static void fam14_ontario_link_data(void)
+{
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+#define AMD_APU_SVID		0x1022
+#define AMD_APU_SSID		0x1234
+
+	/* Define AMD Ontario APU SSID/SVID */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+}
 #endif

asmlinkage void bootblock_c_entry(uint64_t base_timestamp)