Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email )
(
3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ......................................................................
soc/amd/cezanne: Add an option to enable A/B recovery scheme
Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually.
Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B."
The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to enable the A/B recovery layout.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao fishbaozi@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 9 insertions(+), 0 deletions(-)
Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index abeaece..7b97ce7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -408,6 +408,12 @@ help Add psp_verstage signature token to the build & PSP Directory Table
+config PSP_RECOVERY_AB + bool "Use A/B Recovery scheme" + default n + help + Enable the PSP A/B Recovery mechanism + endmenu
config VBOOT diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index adbf3a6..2747622 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -182,6 +182,8 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
+OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ $(OPT_PSP_NVRAM_SIZE) \ @@ -204,6 +206,7 @@ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_RECOVERY_AB) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE)