Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196
-gerrit
commit 8952389e28603efa6b39b60c36a01bec96a5dfd8 Author: Martin Roth gaumless@gmail.com Date: Sun Jan 11 14:29:29 2015 -0700
FSP & CBMEM: Fix broken cbmem CAR transition.
1) Save the pointer to the FSP HOB list to low memory at address 0x614.
This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it.
2) When a request for the pointer to a CAR variable comes in, pass back the location *INSIDE* the FSP hob structure.
3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure.
4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.
Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth gaumless@gmail.com --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/x86/car.c | 34 +++++++++++++++++++--- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index e9cbe43..c05b12b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE
config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 5cd4c65..c090b84 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE
choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..1a95ea1 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -41,13 +41,16 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL;
- +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { char *migrated_base; - int offset; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; + int offset = (char *)var - (char *)_car_start;
/* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -61,6 +64,29 @@ void *car_get_var_ptr(void *var) return var; }
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) +#include <drivers/intel/fsp/fsp_util.h> + /* Before memory is initialized: + * CBMEM_FSP_HOB_PTR == 0xffffffff + * Use CAR - handled above. + * + * After memory is initialized, but before the migration: + * CBMEM_FSP_HOB_PTR is a pointer to the start of the FSP HOB list. + * Use saved CAR area in HOB - handled here. + */ + + if (*(uint32_t *)CBMEM_FSP_HOB_PTR != 0xffffffff) { + /* find the saved temp memory so we can recover cbmem */ + char *saved_tmp_mem_location=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); + + if (saved_tmp_mem_location == NULL) + die("Error: Could not locate Saved CAR memory."); + + return (void *)(saved_tmp_mem_location + offset); + } +#endif + migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS);
if (migrated_base == NULL) { @@ -68,8 +94,6 @@ void *car_get_var_ptr(void *var) return var; }
- offset = (char *)var - (char *)_car_start; - return &migrated_base[offset]; }
@@ -121,7 +145,9 @@ static void do_car_migrate_variables(void) return; }
+#if !IS_ENABLED(PLATFORM_USES_FSP) memcpy(migrated_base, &_car_data_start[0], car_data_size); +#endif
/* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614
#define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 081ea09..3b6d093 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -49,7 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE
config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }