[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block/cse: Add helper functions to CSE lib

[Sridhar Siricilla (Code Review)]

Hello Rizwan Qureshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/35226

to review the following change.

Change subject: src/soc/intel/common/block/cse: Add helper functions to CSE lib
......................................................................

src/soc/intel/common/block/cse: Add helper functions to CSE lib

Below helper function are added:
* wait_cse_rec() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE".
  It's a special CSE mode, the mode ensures CSE does not trigger any
  spi cycles to CSE region.

* set_host_ready() - Clears reset state from host CSR.

Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c
Signed-off-by: Rizwan Qureshi 
Signed-off-by: sridhar 
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 72 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35226/1

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 69cb273..7697a4a 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -67,11 +67,35 @@
 #define MEI_HDR_CSE_ADDR_START	0
 #define MEI_HDR_CSE_ADDR	(((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)

+#define HECI_OP_MODE_SEC_OVERRIDE 5

static struct cse_device {
    uintptr_t sec_bar;
 } g_cse;

+union me_hfs {
+        u32 data;
+        struct {
+        u32 working_state: 4;
+        u32 mfg_mode: 1;
+        u32 fpt_bad: 1;
+        u32 operation_state: 3;
+        u32 fw_init_complete: 1;
+        u32 ft_bup_ld_flr: 1;
+        u32 update_in_progress: 1;
+        u32 error_code: 4;
+        u32 operation_mode: 4;
+        u32 reset_count: 4;
+        u32 boot_options_present: 1;
+        u32 reserved1: 1;
+        u32 bist_test_state: 1;
+        u32 bist_reset_request: 1;
+        u32 current_power_source: 2;
+        u32 d3_support_valid: 1;
+        u32 d0i3_support_valid: 1;
+        } __packed fields;
+};
+
 /*
  * Initialize the device with provided temporary BAR. If BAR is 0 use a
  * default. This is intended for pre-mem usage only where BARs haven't been
@@ -239,6 +263,41 @@
    return csr & CSR_READY;
 }

+
+static int cse_rec(void)
+{
+        union me_hfs hfs;
+        hfs.data = me_read_config32(PCI_ME_HFSTS1);
+        if(hfs.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE)
+                return 1;
+        else
+                return 0;
+}
+
+void set_host_ready(void)
+{
+        uint32_t csr;
+        csr = read_host_csr();
+        csr &= ~CSR_RESET;
+        csr |= CSR_IG;
+        csr |= CSR_READY;
+        write_host_csr(csr);
+}
+
+int wait_cse_rec(void)
+{
+        struct stopwatch sw;
+
+        stopwatch_init_msecs_expire(&sw, 15000);
+        while (!cse_rec()) {
+                udelay(100);
+                if (stopwatch_expired(&sw))
+                        return 0;
+        }
+
+        return 1;
+}
+
 static int wait_heci_ready(void)
 {
    struct stopwatch sw;
@@ -495,11 +554,7 @@

if (wait_heci_ready()) {
    	/* Device is back on its imaginary feet, clear reset */
-		csr = read_host_csr();
-		csr &= ~CSR_RESET;
-		csr |= CSR_IG;
-		csr |= CSR_READY;
-		write_host_csr(csr);
+		set_host_ready();
    	return 1;
    }

diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 9409ce5..82e07cf 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -54,11 +54,22 @@
 int heci_reset(void);

/*
- * Reads config value from a specified offset in the HECI Configuration
+ * Reads and returns config value from a specified offset in the HECI Configuration
  *
  */
 uint32_t me_read_config32(int offset);

+/*
+ * Clears the reset state in the Host CSR
+ */
+void set_host_ready(void);
+
+/*
+ * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
+ * Returns 0 on failure a 1 on success.
+ */
+int wait_cse_rec(void);
+
 #define BIOS_HOST_ADDR							0x00
 #define HECI_MKHI_ADDR							0x07