Isaac Christensen (isaac.christensen@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6865
-gerrit
commit f1efa8c16d149ddba0be759d2db6c0af94857278 Author: Gabe Black gabeblack@google.com Date: Thu Oct 10 02:48:15 2013 -0700
nyan: tegra124: Redestribute the clock code between the mainboard and soc.
There's generic clock initialization that needs to be done for any mainboard using that soc. Other initialization depends on what peripherals are going to be used and what rate they should run at and should be done in the mainboard source.
Change-Id: Idf79faac523bb99f3c7c29bac6947d2149fc3651 Signed-off-by: Gabe Black gabeblack@google.com Reviewed-on: https://chromium-review.googlesource.com/172583 Reviewed-by: Ronald Minnich rminnich@chromium.org Reviewed-by: Julius Werner jwerner@chromium.org Tested-by: Gabe Black gabeblack@chromium.org Commit-Queue: Gabe Black gabeblack@chromium.org (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com --- src/mainboard/google/nyan/bootblock.c | 2 ++ src/soc/nvidia/tegra124/bootblock.c | 4 +-- src/soc/nvidia/tegra124/clock.c | 53 ++++++++++++++++++----------------- src/soc/nvidia/tegra124/clock.h | 6 ++-- 4 files changed, 34 insertions(+), 31 deletions(-)
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index f0753d4..e193ab1 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -18,7 +18,9 @@ */
#include <bootblock_common.h> +#include <soc/nvidia/tegra124/clock.h>
void bootblock_mainboard_init(void) { + clock_config(); } diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cc246c3..f84e48a 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -29,9 +29,9 @@ void main(void) { void *entry;
- set_avp_clock_to_clkm(); + clock_init();
- init_clocks(); + clock_uart_config();
// Serial out, tristate off. pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 563bdae..ff6a2f1 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -148,8 +148,7 @@ static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, return 0; }
- -void init_pllx(void) +static void init_pllx(void) { int osc; struct clk_pll_table *sel; @@ -169,33 +168,41 @@ void init_pllx(void)
adjust_pllp_out_freqs(); } -/* - * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 - * with frequency set at 1MHz. Before initializing PLLP, we need to move the - * system clock's source to CLK_M temporarily. And then switch it to PLLP_out4 - * (204MHz) at a later time. - */ -void set_avp_clock_to_clkm(void) + +void clock_uart_config(void) { - u32 val; + /* Enable clocks to required peripherals. TBD - minimize this list */ + /* The UART is super special so Just Do It right here. */
- val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | - (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | - (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | - (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | - (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clk_rst->crc_sclk_brst_pol); + setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); + setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK); + clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2); udelay(2); + clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); }
/** * The T124 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ -void init_clocks(void) +void clock_init(void) { u32 val;
+ /* + * On poweron, AVP clock source (also called system clock) is set to + * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we + * need to move the system clock's source to CLK_M temporarily. And + * then switch it to PLLP_out4 (204MHz) at a later time. + */ + val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clk_rst->crc_sclk_brst_pol); + udelay(2); + /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1);
@@ -220,16 +227,10 @@ void init_clocks(void)
val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); writel(val, &clk_rst->crc_clk_sys_rate); +}
- /* Enable clocks to required peripherals. TBD - minimize this list */ - /* The UART is super special so Just Do It right here. */ - - setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); - setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK); - clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2); - udelay(2); - clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); - +void clock_config(void) +{ /* fixme. The stupidity of all this ... we are reading and * writing the same register lots of times when we could just * one lousy write with a combined mask. Sigh. diff --git a/src/soc/nvidia/tegra124/clock.h b/src/soc/nvidia/tegra124/clock.h index 39abddb..b97560c 100644 --- a/src/soc/nvidia/tegra124/clock.h +++ b/src/soc/nvidia/tegra124/clock.h @@ -165,13 +165,13 @@ enum { /* make this a macro, rather than a function; let the C compiler find * the error for you if you use an out of range index.. Requires you * to declare a clk_rst pointer. */ -void init_pllx(void); #define clkreset(x) &clk_rst->crc_rst_dev[(x)] #define clkenable(x) &clk_rst->crc_clk_out_enb[(x)] #define clkresetvw(x) &clk_rst->crc_rst_dev_vw[(x)] #define clkenablevw(x) &clk_rst->crc_clk_out_enb_vw[(x)]
-void set_avp_clock_to_clkm(void); -void init_clocks(void); +void clock_uart_config(void); +void clock_config(void); +void clock_init(void);
#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */