Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50893
to look at the new patch set (#2).
Change subject: soc/amd/cezanne/acpi: Add pci0.asl ......................................................................
soc/amd/cezanne/acpi: Add pci0.asl
This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This patches what the Intel platforms are doing. It also matches what linux derives from the e820 tables:
[mem 0xd0000000-0xf7ffffff] available for PCI devices
Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region.
TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f]
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I4ff02012795e2166e3a4197071b1136727089318 --- A src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/acpi/soc.asl M src/soc/amd/cezanne/root_complex.c 3 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/50893/2