Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59519 )
Change subject: security/intel/txt/ramstage.c: Fix HEAP_ACM element size calculation ......................................................................
security/intel/txt/ramstage.c: Fix HEAP_ACM element size calculation
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e --- M src/security/intel/txt/ramstage.c 1 file changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59519/1
diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 217d50c..450cfc5 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -258,7 +258,6 @@
/* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; - data.heap_acm.header.size = sizeof(data.heap_acm); if (data.bdr.bios_sinit_size) { data.heap_acm.num_acms = 2; data.heap_acm.acm_addrs[1] = (uintptr_t)sinit_base; @@ -267,6 +266,19 @@ } data.heap_acm.acm_addrs[0] = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL); + + /* + * FIXME: these calculations handle the lack of SINIT ACM in CBFS. + * Fixed size of the data.heap_acm.acm_addrs array does not allow to + * properly set up the BDR region when SINIT ACM is not present in CBFS. + * Each structure in the data variable defined on the beginning of this + * function should be assembled and appended on the fly taking into + * account the size of given BDR element. + */ + data.heap_acm.header.size = sizeof(data.heap_acm.header) + + sizeof(data.heap_acm.num_acms) + + data.heap_acm.num_acms * sizeof(data.heap_acm.acm_addrs); + /* Extended elements - End marker */ data.end.type = HEAP_EXTDATA_TYPE_END; data.end.size = sizeof(data.end);