Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57051 )
Change subject: soc/amd/common/block/lpc,mb/google/guybrush: Use #defines for eSPI setup ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/bootblock.c:
https://review.coreboot.org/c/coreboot/+/57051/comment/8dcf8290_8fe4676b PS1, Line 51: dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); : dword &= ~(LDRQ0_PD_EN | LDRQ0_EN | BIT(3)); : dword |= LDRQ0_PU_EN; : pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); : : pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); : pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0); : : dword = pm_read32(0x90); : dword |= 1 << 16; : pm_write32(0x90, dword); : : dword = pm_read32(PM_ACPI_CONF); : dword |= 3 << 10; : pm_write32(PM_ACPI_CONF, dword);
Since you are cleaning this up, I think this should be moved to SoC code. […]
I agree. That's part of b/183149183. I did this because we are debugging b/195570693 and was trying to understand what all the pieces were doing.