[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Fix platform reporting in console

[Michael Niewöhner (Code Review)]

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35763 )

Change subject: soc/intel/skylake: Fix platform reporting in console
......................................................................

soc/intel/skylake: Fix platform reporting in console

The 100 series PCH is reported as "SKL" platform which does support SKL
and KBL and thus leads to confusion. Fix the platforms reported in the
console to be reported as "KBL/SKL <pch name>".

Signed-off-by: Michael Niewöhner 
Change-Id: Ida60f619308388adc180a5652908e5a947c17c0f
---
M src/soc/intel/skylake/chip_fsp20.c
1 file changed, 12 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35763/1

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index e46e52c..17bbc31d 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -55,7 +55,7 @@
  * D29:[F0 - F7]		0xA118 - 0xA11F
  * D27:[F0 - F3]		0xA167 - 0xA16A
  */
-static const struct pcie_entry pcie_table_skl_pch_h[] = {
+static const struct pcie_entry pcie_table_spt_pch_h[] = {
    {PCH_DEVFN_PCIE1, 8},
    {PCH_DEVFN_PCIE9, 8},
    {PCH_DEVFN_PCIE17, 4},
@@ -68,7 +68,7 @@
  * D29:[F0 - F7]		0xA298 - 0xA29F
  * D27:[F0 - F7]		0xA2E7 - 0xA2EE
  */
-static const struct pcie_entry pcie_table_kbl_pch_h[] = {
+static const struct pcie_entry pcie_table_unp_pch_h[] = {
    {PCH_DEVFN_PCIE1, 8},
    {PCH_DEVFN_PCIE9, 8},
    {PCH_DEVFN_PCIE17, 8},
@@ -80,7 +80,7 @@
  * D28:[F0 - F7]		0x9D10 - 0x9D17
  * D29:[F0 - F3]		0x9D18 - 0x9D1B
  */
-static const struct pcie_entry pcie_table_skl_pch_lp[] = {
+static const struct pcie_entry pcie_table_spt_pch_lp[] = {
    {PCH_DEVFN_PCIE1, 8},
    {PCH_DEVFN_PCIE9, 4},
 };
@@ -148,17 +148,17 @@
    id_mask = id & ~0xf;
    printk(BIOS_INFO, "Override DT after FSP-S, PCH is ");
    if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) {
-		printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n");
-		pcie_update_device_tree(&pcie_table_skl_pch_lp[0],
-			ARRAY_SIZE(pcie_table_skl_pch_lp));
+		printk(BIOS_INFO, "KBL/SKL Sunrise Point PCH-LP SKU\n");
+		pcie_update_device_tree(&pcie_table_spt_pch_lp[0],
+			ARRAY_SIZE(pcie_table_spt_pch_lp));
    } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) {
-		printk(BIOS_INFO, "KBL PCH-H SKU\n");
-		pcie_update_device_tree(&pcie_table_kbl_pch_h[0],
-			ARRAY_SIZE(pcie_table_kbl_pch_h));
+		printk(BIOS_INFO, "KBL/SKL Sunrise Point PCH-H SKU\n");
+		pcie_update_device_tree(&pcie_table_spt_pch_h[0],
+			ARRAY_SIZE(pcie_table_spt_pch_h));
    } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) {
-		printk(BIOS_INFO, "SKL PCH-H SKU\n");
-		pcie_update_device_tree(&pcie_table_skl_pch_h[0],
-			ARRAY_SIZE(pcie_table_skl_pch_h));
+		printk(BIOS_INFO, "KBL/SKL Union Point PCH-H SKU\n");
+		pcie_update_device_tree(&pcie_table_unp_pch_h[0],
+			ARRAY_SIZE(pcie_table_unp_pch_h));
    } else {
    	printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x"
    		" is not found\n", id);