Duncan Laurie has uploaded a new patch set (#2) to the change originally created by Lijian Zhao. ( https://review.coreboot.org/c/coreboot/+/32089 )
Change subject: soc/intel/cannonlake: Update CPU Ratio base on MSR ......................................................................
soc/intel/cannonlake: Update CPU Ratio base on MSR
The following is the FSP logic: as long as the Cpu Ratio input in coreboot is different with CpuStrapSet, system will force to follow input from coreboot. But CpuStrapsetting is floating, it will be 0 from the first cold boot before memory training and set to 0x1c (or max CPU ratio for the installed CPU) after first memory training.
The previous fix was attempting to ensure settings were cleared when FSP was called in recovery mode, but only when coming from S5 which caused issues if recovery mode is requested by the OS and is only followed by a warm reset.
BUG=b:129412691 TEST=Boot up sarien platform and force recovery, check there's no reset in the path of recovery.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32089/2