Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7130
-gerrit
commit 052667809e8c30fc679d795a8f28996752980e78 Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Oct 19 10:13:14 2014 +0200
sandy/ivy: Remerge interrupt handling
Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/google/butterfly/romstage.c | 42 +------------ src/mainboard/google/link/romstage.c | 39 +----------- src/mainboard/google/parrot/romstage.c | 43 +------------ src/mainboard/google/stout/romstage.c | 43 +------------ src/mainboard/intel/emeraldlake2/romstage.c | 38 +----------- src/mainboard/kontron/ktqm77/romstage.c | 58 +----------------- .../lenovo/t520/acpi/sandybridge_pci_irqs.asl | 64 -------------------- src/mainboard/lenovo/t520/romstage.c | 42 ------------- .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 64 -------------------- src/mainboard/lenovo/t530/romstage.c | 42 ------------- src/mainboard/lenovo/x220/acpi_tables.c | 18 ------ src/mainboard/lenovo/x220/romstage.c | 42 ------------- .../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 64 -------------------- src/mainboard/lenovo/x230/romstage.c | 42 ------------- src/mainboard/samsung/lumpy/romstage.c | 36 +---------- src/mainboard/samsung/stumpy/romstage.c | 38 +----------- .../intel/sandybridge/acpi/hostbridge.asl | 51 +++++++++++++++- src/northbridge/intel/sandybridge/romstage.c | 1 + src/southbridge/intel/bd82x6x/Makefile.inc | 4 ++ src/southbridge/intel/bd82x6x/early_rcba.c | 70 ++++++++++++++++++++++ src/southbridge/intel/bd82x6x/madt.c | 45 ++++++++++++++ src/southbridge/intel/bd82x6x/pch.h | 2 + 22 files changed, 179 insertions(+), 709 deletions(-)
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 908b6d8..7528dec 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -62,47 +62,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 8236e20..f90d7e7 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -78,44 +78,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P3IP WLAN INTA -> PIRQB - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * TRACKPAD -> PIRQE (Edge Triggered) - * TOUCHSCREEN -> PIRQG (Edge Triggered) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ce42b41..c25b419 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -62,48 +62,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQB - * D28IP_P3IP ETH0 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQE - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * - * Trackpad DVT PIRQA (16) - * Trackpad DVT PIRQE (20) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index bfa4af7..16ce978 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -68,48 +68,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D20IP_XHCI XHCI INTA -> PIRQD (MSI) - * D26IP_E2P EHCI #2 INTA -> PIRQF - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQD - * D28IP_P3IP Card Reader INTB -> PIRQE - * D28IP_P6IP LAN INTC -> PIRQB - * D29IP_E1P EHCI #1 INTA -> PIRQD - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); - DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 220b1d7..d50093e 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -73,43 +73,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 401314c..bfe7715 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -59,63 +59,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * D31IP_TTIP THRT INTC -> PIRQC - * D31IP_SIP2 SATA2 NOINT - * D31IP_SMIP SMBUS INTC -> PIRQC - * D31IP_SIP SATA INTB -> PIRQD (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQH - * D28IP_P8IP Slot? INTD -> PIRQD - * D28IP_P7IP PCIEx1 INTC -> PIRQC - * D28IP_P6IP 1394 INTB -> PIRQB (MSI) - * D28IP_P5IP GbEPHY INTA -> PIRQA - * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) - * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) - * D28IP_P2IP Slot? INTB -> PIRQB - * D28IP_P1IP Slot? INTA -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * D26IP_E2P EHCI2 INTA -> PIRQA - * D25IP_LIP ETH0 INTA -> PIRQE (MSI) - * D22IP_KTIP MEI NOINT - * D22IP_IDERIP MEI NOINT - * D22IP_MEI2IP MEI NOINT - * D22IP_MEI1IP MEI NOINT - * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) - * GFX INTA -> PIRQA (MSI) - * PEGx16 INTA -> PIRQA - * INTB -> PIRQB - * INTC -> PIRQC - * INTD -> PIRQD - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | - (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) | - (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (INTA << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); - DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); - DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); - DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index b4b81a2..0000000 --- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 83be0c7..f7866a8 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -60,48 +60,6 @@ void pch_enable_lpc(void)
void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQB - * D28IP_P4IP EXC INTB -> PIRQF - * D28IP_P5IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) | - (INTC << D28IP_P5IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1ee51fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6c1c695..0000000 --- a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 115f83b..0a49ed0 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -47,48 +47,6 @@ void pch_enable_lpc(void)
void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); }
-unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index ba48fac..d9c8aa0 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -57,48 +57,6 @@ void pch_enable_lpc(void)
void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1fe41fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6c1c695..0000000 --- a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 2c39741..0bb137e 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -60,48 +60,6 @@ void pch_enable_lpc(void)
void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index dc4161d..f37e87e 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -75,41 +75,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQB - * D31IP_SIP SATA INTA -> PIRQA (MSI) - * D31IP_SMIP SMBUS INTC -> PIRQH - * D31IP_TTIP THRT INTB -> PIRQG - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * - * LIGHTSENSOR -> PIRQE (Edge Triggered) - * TRACKPAD -> PIRQF (Edge Triggered) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + southbridge_configure_default_intmap();
/* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 625903d..2c651ae 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -87,43 +87,7 @@ static void rcba_config(void) { u32 reg32;
- /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 690c072..4025a0f 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -379,5 +379,52 @@ Method (_CRS, 0, Serialized) Return (MCRS) }
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/sandybridge_pci_irqs.asl" +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // XHCI 0:14.0 (ivy only) + Package() { 0x0014ffff, 0, 0, 19 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 (ivy only) + Package() { 0x0014ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 67c64d7..902d66d 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -91,6 +91,7 @@ void main(unsigned long bist) timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c);
+ southbridge_configure_default_intmap(); rcba_config(); post_code(0x3d);
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 3d33edc..08e5054 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -50,12 +50,16 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_smbus.c me_status.c gpio.c romstage-y += reset.c romstage-y += early_spi.c early_pch.c +romstage-y += early_rcba.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
+ramstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += madt.c +ramstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += madt.c + ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c new file mode 100644 index 0000000..e26d007 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "pch.h" +#include "northbridge/intel/sandybridge/sandybridge.h" + +void +southbridge_configure_default_intmap(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP SLOT1 INTA -> PIRQB + * D28IP_P2IP SLOT2 INTB -> PIRQF + * D28IP_P3IP SLOT3 INTC -> PIRQD + * D28IP_P5IP SLOT5 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); +} diff --git a/src/southbridge/intel/bd82x6x/madt.c b/src/southbridge/intel/bd82x6x/madt.c new file mode 100644 index 0000000..45b652b --- /dev/null +++ b/src/southbridge/intel/bd82x6x/madt.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 9b84c67..8147559 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,6 +75,8 @@ void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); +void +southbridge_configure_default_intmap(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void);