[coreboot-gerrit] [S] Change in coreboot[master]: mb/system76: Enable C10 reporting on systems using eSPI

[Tim Crawford (Code Review)]

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76910?usp=email )

Change subject: mb/system76: Enable C10 reporting on systems using eSPI
......................................................................

mb/system76: Enable C10 reporting on systems using eSPI

Report CPU C10 state over eSPI so that the EC can use Virtual Wires to
detect if PECI can be used.

Change-Id: I301361f35caee8ba1c3fd9227219603897add92b
Signed-off-by: Tim Crawford 
---
M src/mainboard/system76/adl/ramstage.c
M src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
M src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
M src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
4 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/76910/1

diff --git a/src/mainboard/system76/adl/ramstage.c b/src/mainboard/system76/adl/ramstage.c
index c767f2d..aa9a1b7 100644
--- a/src/mainboard/system76/adl/ramstage.c
+++ b/src/mainboard/system76/adl/ramstage.c
@@ -17,6 +17,9 @@
    params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13

params->SataPortsSolidStateDrive[1] = 1;
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }

static void mainboard_init(void *chip_info)
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
index 9d98563..b4106df 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
@@ -18,4 +18,7 @@

// Remap PEG2 as PEG1
    params->CpuPcieRpFunctionSwap = 1;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
index 0f83461..1623225 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
@@ -15,4 +15,7 @@
    params->CpuPcieRpAdvancedErrorReporting[1] = 0;
    params->CpuPcieRpLtrEnable[1] = 1;
    params->CpuPcieRpPtmEnabled[1] = 0;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
index 72ad3fc..a4d4b40 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
@@ -21,4 +21,7 @@

// Low latency legacy I/O
    params->PchLegacyIoLowLatency = 1;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }