[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Use official microcodes

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81637?usp=email )

Change subject: soc/intel/xeon_sp/spr: Use official microcodes
......................................................................

soc/intel/xeon_sp/spr: Use official microcodes

Use the official microcode updates from intel-microcode submodule
by default. Downstream users can still decide to use their own files.

Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/Makefile.mk
2 files changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/81637/1

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 18efbe5..af3e8eb 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -3,7 +3,6 @@
 config SOC_INTEL_SAPPHIRERAPIDS_SP
    bool
    select FSP_NVS_DATA_POST_SILICON_INIT
-	select MICROCODE_BLOB_NOT_HOOKED_UP
    select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
    select DISABLE_ACPI_HIBERNATE
    select DEFAULT_X2APIC_RUNTIME
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index d288df6..a3d6af5 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -19,4 +19,7 @@
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr

+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02
+
 endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP