[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43657 )

Change subject: soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43657/4/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43657/4/src/soc/intel/tigerlake/rom... 
PS4, Line 200: m_cfg->TcssDma0En || m_cfg->TcssDma1En
> I think this should be (m_cfg->TcssItbtPcie0En || m_cfg->TcssItbtPcie1En || m_cfg->TcssItbtPcie2En | […]

TcssDma0 is grouped with Pcie root ports 0/1 and TcssDma1 together with Pcie 2/3. fsp refers
to VtdItbtEnable along with Pcie 0/1/2/3 enabling(through m_cfg->TcssItbtPcieXEn) while configuring Vtd->BaseAddress (fsp: ConfigureITbtVtBar function). It seems proper for VtdItbtEnable to be based on TcssDma0 and TcssDma1 enabling.