[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Michael Niewöhner (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 49:

(1 comment)

Patchset:

PS46:
> > @Nico I wonder how you want to integrate that minimal sample exactly. That minimal sample code should be in the Zephyr project IMO, so we might add it to 3rdparty/Zephyr and build it like other external stuff (payloads, libgfxinit). Is that what you have in mind?
>
> IMHO, Zephyr would be complete overkill. And I've also talked to Werner, it's
> not what they want. I would add a stub to coreboot that is enough to boot. So
> when needed (e.g. for these ethernet MACs) we can easily add configuration
> code to it. If somebody wants to do more with the PSE beside silicon init,
> we can still discuss that later ;)
>
> From a coreboot perspective, we could treat the PSE as just another AP.
> Unfortunately the only one that has access to all the registers of its
> peripherals and hence needs to do part of ramstage's job or at least act
> as a broker.
>
> Of course, having the Zephyr code published would answer what we have to
> do to talk to FSP and get these MACs running.

I fully agree. The idea was just to have *something* this minimal stub can be based on.

However, for booting nothing is required, when the UPD is set (PchPseEnable). So, what about another change adding this UPD (set to 0) first?