Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63654 )
Change subject: soc/alderlake: Add ADL-S PCIe support ......................................................................
soc/alderlake: Add ADL-S PCIe support
Extend the code to support ADL-S PCIe Root Ports. Based on DOC #619362 and #619501.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 --- M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/pci_devs.h M src/soc/intel/alderlake/pcie_rp.c 4 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/63654/1
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 699b39d..4bb7aa7 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -63,6 +63,7 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; + case SA_DEVFN_CPU_PCIE1_1: return "PEG3"; case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; case SA_DEVFN_IGD: return "GFX0"; @@ -98,6 +99,25 @@ case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_PCIE17: return "RP17"; + case PCH_DEVFN_PCIE18: return "RP18"; + case PCH_DEVFN_PCIE19: return "RP19"; + case PCH_DEVFN_PCIE20: return "RP20"; + case PCH_DEVFN_PCIE21: return "RP21"; + case PCH_DEVFN_PCIE22: return "RP22"; + case PCH_DEVFN_PCIE23: return "RP23"; + case PCH_DEVFN_PCIE24: return "RP24"; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + /* Avoid conflicts with PCH-N eMMC */ + case PCH_DEVFN_PCIE25: return "RP25"; + case PCH_DEVFN_PCIE26: return "RP26"; + case PCH_DEVFN_PCIE27: return "RP27"; + case PCH_DEVFN_PCIE28: return "RP28"; +#endif case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index fa4104e..0d72484 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -214,8 +214,38 @@ FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D), +#endif }, }, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + { + .slot = PCH_DEV_SLOT_PCIE_2, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCH_DEV_SLOT_PCIE_3, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE25, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE26, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE27, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE28, PCI_INT_D, PIRQ_D), + }, + }, +#endif { .slot = PCH_DEV_SLOT_SIO5, .fns = { diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index b7196df..8041bc5 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -27,6 +27,7 @@
#define SA_DEV_SLOT_CPU_1 0x01 #define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0) +#define SA_DEVFN_CPU_PCIE1_1 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 1)
#define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) @@ -195,10 +196,47 @@ #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) +#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) +#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) +#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) +#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) +#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) +#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) +#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) + + +#define PCH_DEV_SLOT_PCIE_2 0x1b +#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) +#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) +#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) +#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) +#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) +#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) +#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) +#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) +#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) +#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) +#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) +#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) +#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) +#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) +#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) +#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) + +#define PCH_DEV_SLOT_PCIE_3 0x1a +#define PCH_DEVFN_PCIE25 _PCH_DEVFN(PCIE_3, 0) +#define PCH_DEVFN_PCIE26 _PCH_DEVFN(PCIE_3, 1) +#define PCH_DEVFN_PCIE27 _PCH_DEVFN(PCIE_3, 2) +#define PCH_DEVFN_PCIE28 _PCH_DEVFN(PCIE_3, 3) +#define PCH_DEV_PCIE25 _PCH_DEV(PCIE_3, 0) +#define PCH_DEV_PCIE26 _PCH_DEV(PCIE_3, 1) +#define PCH_DEV_PCIE27 _PCH_DEV(PCIE_3, 2) +#define PCH_DEV_PCIE28 _PCH_DEV(PCIE_3, 3)
#define PCH_DEV_SLOT_SIO5 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 1193047..6bbe298 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -20,11 +20,22 @@ { 0 } };
+static const struct pcie_rp_group pch_s_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_3, .count = 4, .lcap_port_base = 1 }, + { 0 } +}; + const struct pcie_rp_group *get_pch_pcie_rp_table(void) { if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) return pch_m_rp_groups;
+ if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + return pch_s_rp_groups; + return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */ }
@@ -50,6 +61,12 @@ { 0 } };
+static const struct pcie_rp_group cpu_s_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 }, + { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 2, .lcap_port_base = 1 }, + { 0 } +}; + const struct pcie_rp_group *get_cpu_pcie_rp_table(void) { if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) @@ -58,6 +75,9 @@ if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) return cpu_n_rp_groups;
+ if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + return cpu_s_rp_groups; + return cpu_rp_groups; }