[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp/skx: Fix CPU init

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85289?usp=email )

Change subject: soc/intel/xeon_sp/skx: Fix CPU init
......................................................................

soc/intel/xeon_sp/skx: Fix CPU init

Move CPU init closer to other SoC and CPX.

FSP-S only is aware of socket 0, thus all cores must rerun all
settings already done by FSP, in order to set up socket 1 as well.

FSP sets the following on socket0:
- Set BIT20 in MSR_VR_MISC_CONFIG
- Set LTR_IIO_DISABLE in MSR_POWER_CTL

Lock the following MSRs:
- MSR_SNC_CONFIG
- MSR_CONFIG_TDP_CONTROL
- MSR_FEATURE_CONFIG
- MSR_TURBO_ACTIVATION_RATIO

Also do the following as done on other SoCs:
- Configure VMX and lock it
- Enable LAPIC TPRs (fixes MWAIT support)
- Honor CONFIG_SET_MSR_AESNI_LOCK_BIT
- Set TCC thermal target as set in devicetree

Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT.

TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in
      ACPI C6, no boot delay or hung tasks could be found.

Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85289
Reviewed-by: Christian Walter 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/xeon_sp/include/soc/msr.h
M src/soc/intel/xeon_sp/skx/cpu.c
3 files changed, 36 insertions(+), 9 deletions(-)

Approvals:
  Christian Walter: Looks good to me, approved
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 1770167..c077fb8 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -320,7 +320,7 @@
     */
    if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) ||
        CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) ||
-	    CONFIG(SOC_INTEL_BROADWELL))
+	    CONFIG(SOC_INTEL_BROADWELL) || CONFIG(SOC_INTEL_SKYLAKE_SP))
    	return;

/* Time Window Tau Bits [6:0] */
diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h
index 19c37f6..09f1acc 100644
--- a/src/soc/intel/xeon_sp/include/soc/msr.h
+++ b/src/soc/intel/xeon_sp/include/soc/msr.h
@@ -8,6 +8,8 @@
 #define MSR_FEATURE_CONFIG              0x13c
 #define   FEATURE_CONFIG_LOCK           BIT(0)

+#define MSR_SNC_CONFIG                  0x152
+
 #define IA32_MCG_CAP                    0x179
 #define IA32_MCG_CAP_COUNT_MASK         0xff
 #define IA32_MCG_CAP_CTL_P_BIT          8
@@ -71,7 +73,6 @@
 #define MSR_TURBO_ACTIVATION_RATIO   0x64c
 #define MAX_NON_TURBO_RATIO_SHIFT    0
 #define MAX_NON_TURBO_RATIO          (0xff << MAX_NON_TURBO_RATIO_SHIFT)
-
 #define IA32_PM_ENABLE 0x770
 #define IA32_HWP_CAPABILITIES 0x771

diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index fc49ddc..36dc63b 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -7,6 +7,7 @@
 #include <cpu/intel/cpu_ids.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/mp.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/intel/smm_reloc.h>
@@ -84,15 +85,18 @@
           cpu->path.apic.package_id);
    assert(chip_config);

-	/* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/
+	/* set MSR_PKG_CST_CONFIG_CONTROL - scope per core */
    msr.hi = 0;
    msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE);
    wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);

/* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */
    msr = rdmsr(MSR_POWER_CTL);
-	msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE
-		| PROCHOT_LOCK_ENABLE);
+	msr.lo &= ~(POWER_CTL_C1E_MASK | BIT2);
+	msr.lo |= ENERGY_PERF_BIAS_ACCESS_ENABLE;
+	msr.lo |= PWR_PERF_TUNING_DYN_SWITCHING_ENABLE;
+	msr.lo |= LTR_IIO_DISABLE;
+	msr.lo |= PROCHOT_LOCK_ENABLE;
    wrmsr(MSR_POWER_CTL, msr);

/* Set P-State ratio */
@@ -115,7 +119,9 @@
    	wrmsr(MSR_MISC_PWR_MGMT, msr);
    }

-	/* TODO MSR_VR_MISC_CONFIG */
+	msr = rdmsr(MSR_VR_MISC_CONFIG);
+	msr.hi |= BIT20;
+	wrmsr(MSR_VR_MISC_CONFIG, msr);

/* Set current limit lock */
    msr = rdmsr(MSR_VR_CURRENT_CONFIG);
@@ -132,14 +138,19 @@
    msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff;
    wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr);

-	/* set Turbo Activation ratio */
-	msr.hi = 0;
+	/* set Turbo Activation ratio - scope package */
    msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
    msr.lo |= MAX_NON_TURBO_RATIO;
+	msr.lo |= BIT31;	/* Lock it */
    wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);

-	/* Enable Fast Strings */
+	/* Scope package */
+	msr = rdmsr(MSR_CONFIG_TDP_CONTROL);
+	msr.lo |= BIT31;	/* Lock it */
+	wrmsr(MSR_CONFIG_TDP_CONTROL, msr);
+
    msr = rdmsr(IA32_MISC_ENABLE);
+	/* Enable Fast Strings */
    msr.lo |= FAST_STRINGS_ENABLE_BIT;
    wrmsr(IA32_MISC_ENABLE, msr);

@@ -149,9 +160,18 @@
    msr.hi = 0;
    wrmsr(MSR_IA32_ENERGY_PERF_BIAS, msr);

+	if (!intel_ht_sibling()) {
+		/* scope per core */
+		msr = rdmsr(MSR_SNC_CONFIG);
+		msr.lo |= BIT28;	/* Lock it */
+		wrmsr(MSR_SNC_CONFIG, msr);
+	}
+
    /* Enable Turbo */
    enable_turbo();

+	configure_tcc_thermal_target();
+
    /* Enable speed step. */
    if (get_turbo_state() == TURBO_ENABLED) {
    	msr = rdmsr(IA32_MISC_ENABLE);
@@ -161,6 +181,12 @@

/* Clear out pending MCEs */
    xeon_configure_mca();
+
+	/* Enable Vmx */
+	set_vmx_and_lock();
+	set_aesni_lock();
+
+	enable_lapic_tpr();
 }

static struct device_operations cpu_dev_ops = {