[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Saurabh Mishra (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 23:

(4 comments)

Patchset:

PS19:
> > *to […]

Hi Subrata, we are using same for PTL as well, "UDK_202302_BINDING"

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/268ab4ec_2da71b37?usp... :
PS22, Line 10: 	select PLATFORM_USES_FSP2_4
> kindly follow the order (this is help)

Done

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/87fa259b_ed7b373f?usp... :
PS22, Line 74: 0x4010800000
> if possible, please specify the magic calculation that you have used here to derive the IOM BAR

we have used below macro.
((long int) Ps2bMmioBase | (int) (((Offset) & 0x0F0000) << 8) | ((unsigned char)(Pid) << 16) | (short int) ((Offset) & 0xFFFF))

Where, Ps2bMmioBase = 0x4010000000, Offset = 0x0, Pid = 0x80

https://review.coreboot.org/c/coreboot/+/83354/comment/a760a498_68b10ecf?usp... :
PS22, Line 76: 0x401080FFFF
> (IOM_BASE_ADDR + IOM_BASE_SIZE - 1)

The value is correct, 0x401080FFFF = ((0x4010800000 + 0x10000) -1)