[coreboot-gerrit] [S] Change in coreboot[master]: drivers/intel/fsp2_0: Create config option to handle broken FSP API

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74782 )

Change subject: drivers/intel/fsp2_0: Create config option to handle broken FSP API
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drivers/intel/fsp2_0: Create config option to handle broken FSP API

This patch applies a workaround to fix an issue where FSP
MultiPhaseSIInit API is unable to return the ERROR status to the
bootloader upon exiting. As a result, it affects the platform stability
where silicon reference code is expecting a reset (warm/cold/global) to
complete the chipset initialization process but unfortunately as
bootloader is unable to understand the return status in proper, it
failed to take required action to meet the silicon reference code
requirement.

This patch is the base code which just adds the config option to allow
the target SoC platform to apply this W/A if the problem existed inside
the FSP MultiPhaseSiInit.

At present the problem has only been reported with Alder Lake and
Raptor Lake FSP where MultiPhaseSiInit API is unable to return any
ERROR status.

ADL/RPL FSP is already in the post PV phase where the ETA to fix
problems properly inside the FSP is not known. Additionally, MTL FSP
doesn't exhibit this problem hence, most likely this solution is only
for ADL/RPL SoC based platform.

BUG=b:278665768
TEST=No functional impact as this patch just added the config option.

Signed-off-by: Subrata Banik 
Change-Id: I3b15ef5b50fe1fe73bf9ad0aa4be90aae07ebf73
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74782/1

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 2132737..378f4fb 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -389,4 +389,17 @@
      Save MRC training data after FSP-S. Select this on platforms that generate MRC
      cache HOB data as part of FSP-S rather than FSP-M.

+config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
+	bool
+	default n
+	depends on PLATFORM_USES_FSP2_2
+	help
+	  Select this config for Intel SoC platform where FSP MultiPhaseSiInit API is unable
+	  to return ERROR status properly.
+
+	  The config option will be selected based on the target SoC platform and if the
+	  problem existed inside the FSP MultiPhaseSiInit. At present the problem has only
+	  reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable
+	  to return any ERROR status.
+
 endif