Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18491
-gerrit
commit 8f3cfe00e2a87e9882f97e1a3e6d195cb0f894cc Author: Aaron Durbin adurbin@chromium.org Date: Fri Feb 24 15:56:27 2017 -0600
mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state
The cr50 part on reef is connected to the SoC's UART lines. However, when the tx signal is low it causes an interrupt to fire on cr50. Therefore, keep the tx signal high in suspend state so that it doesn't cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283 BRANCH=reef TEST=s0ix no longer causes interrupt storm on cr50. Power consumption normal.
Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/reef/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index a9a6248..ae89da1 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -327,7 +327,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */