[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: fix eSPI virtual wire polarity encoding

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43010 )

Change subject: soc/amd/common: fix eSPI virtual wire polarity encoding
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43010/1/src/soc/amd/common/block/in... 
File src/soc/amd/common/block/include/amdblocks/espi.h:

https://review.coreboot.org/c/coreboot/+/43010/1/src/soc/amd/common/block/in... 
PS1, Line 46: eSPI interrupts are active level high signals
Is this defined in the eSPI spec? I don't remember seeing that.