[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brox/var/lotso: GPP_A17 used for RT522A VDD

[Jian Tong (Code Review)]

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84254?usp=email )

Change subject: mb/google/brox/var/lotso: GPP_A17 used for RT522A VDD
......................................................................

mb/google/brox/var/lotso: GPP_A17 used for RT522A VDD

BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a
Signed-off-by: Jian Tong 
---
M src/mainboard/google/brox/variants/lotso/gpio.c
M src/mainboard/google/brox/variants/lotso/overridetree.cb
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/84254/1

diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c
index 0b98286..d5abe8c 100644
--- a/src/mainboard/google/brox/variants/lotso/gpio.c
+++ b/src/mainboard/google/brox/variants/lotso/gpio.c
@@ -7,6 +7,8 @@

/* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {
+	/* GPP_D03 : [] ==> EN_PP3300_SD */
+	PAD_CFG_GPO_LOCK(GPP_A17, 1, LOCK_CONFIG),
    /* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6
     * NF6: USB_C_GPP_B14] ==> ACZ_SPKR */
    PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 85a3506..bf1a2f4 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -358,6 +358,7 @@
    			.pcie_rp_aspm = ASPM_L1,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A17)"
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
    			register "enable_delay_ms" = "1"
    			register "srcclk_pin" = "3"