[coreboot-gerrit] Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform DDR init

[T.Michael Turney (Code Review)]

Hello mturney mturney, Julius Werner, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/25208

to look at the new patch set (#71).

Change subject: sdm845: Add QCLib to RomStage to perform DDR init
......................................................................

sdm845: Add QCLib to RomStage to perform DDR init

CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
 DDR Training data
 QCLib serial console output
 DDR Information (base & size)
 limits cfg data

TEST=build & run

Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney 
---
M src/mainboard/google/cheza/chromeos.fmd
M src/mainboard/google/cheza/romstage.c
M src/soc/qualcomm/sdm845/Kconfig
M src/soc/qualcomm/sdm845/Makefile.inc
M src/soc/qualcomm/sdm845/include/soc/memlayout.ld
M src/soc/qualcomm/sdm845/include/soc/mmu.h
A src/soc/qualcomm/sdm845/include/soc/qclib.h
M src/soc/qualcomm/sdm845/include/soc/symbols.h
M src/soc/qualcomm/sdm845/mmu.c
A src/soc/qualcomm/sdm845/qclib_execute.c
M src/soc/qualcomm/sdm845/soc.c
11 files changed, 460 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/25208/71