Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61504 )
Change subject: nb/intel/haswell: Report SMBIOS memory frequency in MT/s ......................................................................
nb/intel/haswell: Report SMBIOS memory frequency in MT/s
The memory frequency values in SMBIOS tables are expressed in MT/s, not MHz. Adjust the reported frequency values accordingly.
Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell_mrc/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/61504/1
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index e46eb57..fedb683 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -234,7 +234,7 @@
memset(mem_info, 0, sizeof(struct memory_info));
- const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; + const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
for (ch = 0; ch < NUM_CHANNELS; ch++) { const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); @@ -246,7 +246,7 @@ dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = ddr_frequency; + dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); dimm->channel_num = ch; dimm->dimm_num = d_num;