build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44713 )
Change subject: soc/mediatek/mt8192: Add dramc ac timing setting ......................................................................
Patch Set 1:
(12 comments)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 4042: u8 tref_bw = 0, tfaw_05t=0, trrd_05t=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 4042: u8 tref_bw = 0, tfaw_05t=0, trrd_05t=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 4044: u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 4044: u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 4044: u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 4044: u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 9: static void dramc_ac_timing_optimize(const struct ddr_cali* cali) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 43: struct optimize_ac_time tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] = { space prohibited before open square bracket '['
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 77: {.trfc = 100, .trfc_05t = 0, .trfc_pb = 44, .trfrc_pb05t = 0, .tx_ref_cnt = 115}, line over 96 characters
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 83: {.trfc = 137, .trfc_05t = 1, .trfc_pb = 63, .trfrc_pb05t = 0, .tx_ref_cnt = 154}, line over 96 characters
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 145: SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFC_05T, trfc_05t); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44713/1/src/soc/mediatek/mt8192/dra... PS1, Line 148: SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); line over 96 characters