[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macros

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61398 )

Change subject: nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macros
......................................................................

nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macros

Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width'

Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_mrc.c
1 file changed, 5 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 186ab59..0a7d192 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -14,6 +14,7 @@
 #include <device/pci_def.h>
 #include <lib.h>
 #include <mrc_cache.h>
+#include <smbios.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <timestamp.h>
@@ -413,7 +414,7 @@
    	if (dimm_size) {
    		dimm = &mem_info->dimm[dimm_cnt];
    		dimm->dimm_size = dimm_size;
-			dimm->ddr_type = 0x18;				/* DDR3 */
+			dimm->ddr_type = MEMORY_TYPE_DDR3;
    		dimm->ddr_frequency = ddr_frequency;
    		dimm->rank_per_dimm = 1 + ((ch_conf >> 17) & 1);
    		dimm->channel_num = i;
@@ -429,7 +430,7 @@
    			(pei_data->spd_data[0][118] << 8) |
    			(pei_data->spd_data[0][117] & 0xFF);
    		dimm->mod_type = 3;				/* SPD_SODIMM */
-			dimm->bus_width = 0x3;				/* 64-bit */
+			dimm->bus_width = MEMORY_BUS_WIDTH_64;
    		dimm_cnt++;
    	}
    	/* DIMM-B */
@@ -437,7 +438,7 @@
    	if (dimm_size) {
    		dimm = &mem_info->dimm[dimm_cnt];
    		dimm->dimm_size = dimm_size;
-			dimm->ddr_type = 0x18;				/* DDR3 */
+			dimm->ddr_type = MEMORY_TYPE_DDR3;
    		dimm->ddr_frequency = ddr_frequency;
    		dimm->rank_per_dimm =  1 + ((ch_conf >> 18) & 1);
    		dimm->channel_num = i;
@@ -453,7 +454,7 @@
    			(pei_data->spd_data[0][118] << 8) |
    			(pei_data->spd_data[0][117] & 0xFF);
    		dimm->mod_type = 3;				/* SPD_SODIMM */
-			dimm->bus_width = 0x3;				/* 64-bit */
+			dimm->bus_width = MEMORY_BUS_WIDTH_64;
    		dimm_cnt++;
    	}
    }