Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )
Change subject: arch/x86: Cache the TSEG region at the top of ram
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Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34995/9/src/arch/x86/postcar_loader...
File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34995/9/src/arch/x86/postcar_loader...
PS9, Line 203: return;
will wait for Aaron to reply as its been originally done in that way
@Aaron, if you could take a further look on this. Do you think keeping in common place helps or should i move this into 3 cl as its been done previously ?
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