[coreboot-gerrit] Change in coreboot[master]: src/security/vboot: Add Support for Intel PTT

[Christian Walter (Code Review)]

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34510 )

Change subject: src/security/vboot: Add Support for Intel PTT
......................................................................

src/security/vboot: Add Support for Intel PTT

Add support for Intel PTT. For supporting Intel PTT we need to disable
read and write access to the TPM NVRAM during the bootblock. TPM NVRAM
will only be available once the DRAM is initialized. To circumvent this,
we mock secdata if HAVE_INTEL_PTT is set. The underlying problem is,
that the iTPM only supports a stripped down instruction set while the
Intel ME is not fully booted up. Details can be found in Intel document
number 571993 - Paragraph 2.10.

Change-Id: I08c9a839f53f96506be5fb68f7c1ed5bf6692505
Signed-off-by: Christian Walter 
---
M src/security/vboot/Kconfig
M src/security/vboot/secdata_tpm.c
2 files changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34510/1

diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig
index fa98935..ac0c09d 100644
--- a/src/security/vboot/Kconfig
+++ b/src/security/vboot/Kconfig
@@ -26,6 +26,9 @@

if VBOOT

+comment "Anti-Rollback Protection disabled due to Intel PTT"
+	depends on HAVE_INTEL_PTT
+
 config VBOOT_MEASURED_BOOT
    bool "Enable Measured Boot"
    default n
diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c
index 39cd614..6e3cdf7 100644
--- a/src/security/vboot/secdata_tpm.c
+++ b/src/security/vboot/secdata_tpm.c
@@ -274,11 +274,17 @@

uint32_t antirollback_lock_space_firmware(void)
 {
+	if (CONFIG(HAVE_INTEL_PTT))
+		return VB2_SUCCESS;
+
    return tlcl_lock_nv_write(FIRMWARE_NV_INDEX);
 }

uint32_t antirollback_lock_space_rec_hash(void)
 {
+	if (CONFIG(HAVE_INTEL_PTT))
+		return VB2_SUCCESS;
+
    return tlcl_lock_nv_write(REC_HASH_NV_INDEX);
 }

@@ -462,6 +468,12 @@
    if (rv)
    	return rv;

+	/* If we are using Intel PTT, we do not have antirollback protection. */
+	if (CONFIG(HAVE_INTEL_PTT)) {
+		vb2api_secdata_create(ctx);
+		return VB2_SUCCESS;
+	}
+
    /* Read the firmware space. */
    rv = read_space_firmware(ctx);
    if (rv == TPM_E_BADINDEX) {
@@ -481,6 +493,8 @@

uint32_t antirollback_write_space_firmware(struct vb2_context *ctx)
 {
+	if (CONFIG(HAVE_INTEL_PTT))
+		return VB2_SUCCESS;
    if (CONFIG(CR50_IMMEDIATELY_COMMIT_FW_SECDATA))
    	tlcl_cr50_enable_nvcommits();
    return write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE);
@@ -488,6 +502,9 @@

uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size)
 {
+	if (CONFIG(HAVE_INTEL_PTT))
+		return VB2_SUCCESS;
+
    if (size != REC_HASH_NV_SIZE) {
    	VBDEBUG("TPM: Incorrect buffer size for rec hash. "
    		"(Expected=0x%x Actual=0x%x).\n", REC_HASH_NV_SIZE,
@@ -499,6 +516,9 @@

uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size)
 {
+	if (CONFIG(HAVE_INTEL_PTT))
+		return VB2_SUCCESS;
+
    uint8_t spc_data[REC_HASH_NV_SIZE];
    uint32_t rv;