Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35226 )
Change subject: src/soc/intel/common/block/cse: Make hfsts1 common & add helper functions
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Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35226/25//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/35226/25//COMMIT_MSG@9
PS25, Line 9: Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs,
But is FWSTS1 the same for APL as well?
There is one difference, for APL/GLK bit 25 and 26 are as below.
Bist Test Result[26]
Bist Test State[25]
Will add fix to include APL as well
#if CONFIG(SOC_INTEL_APOLLOLAKE)
u32 bist_test_state: 1;
u32 bist_test_result: 1;
#else
u32 reserved1: 1;
u32 bist_test_state: 1;
#endif
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Gerrit-Project: coreboot
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