[coreboot-gerrit] Change in ...coreboot[master]: drivers/tpm: update TPM initialization logic for Intel FSP2.0

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31837 )

Change subject: drivers/tpm: update TPM initialization logic for Intel FSP2.0
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Patch Set 3:

Just a short question. Why is the MRC cache bound to the TPM?? Is there any specific security mechanism involved. The first time I looked at the code I got the impression we can do better storing stuff in the spi flash