[coreboot-gerrit] Patch merged into coreboot/master: b774313 exynos5420: get rid of old exynos5420_config_l2_cache()

the following patch was just integrated into master:
commit b77431336e44ba9721f18220e2a7dedafe250528
Author: David Hendricks 
Date:   Fri Aug 9 18:19:29 2013 -0700

exynos5420: get rid of old exynos5420_config_l2_cache()

We set up L2 cache early in romstage now so the old
    function is now redundant.

Signed-off-by: David Hendricks

Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
    Reviewed-on: https://gerrit.chromium.org/gerrit/65428
    Reviewed-by: Hung-Te Lin 
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    (cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f)

exynos: stack size: Increase the stack size to 16KB.

The lzma decoding function in the RAM stage allocates nearly 16KB on the stack
    which is shared between the bootblock, rom stage, and ram stage. The stack had
    been much too small and needed to be expanded.

Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868
    Signed-off-by: Gabe Black 
    Reviewed-on: https://gerrit.chromium.org/gerrit/65937
    Reviewed-by: Ronald G. Minnich 
    Tested-by: Gabe Black 
    Commit-Queue: Gabe Black 
    (cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b)

exynos: gpio: add a bigger delay when reading board strappings

Z-state pins were not reading reliably with a 5us delay, so increase
    it to 15us.

This is ported from https://gerrit.chromium.org/gerrit/64338

Signed-off-by: David Hendricks

Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35
    Reviewed-on: https://gerrit.chromium.org/gerrit/65727
    Reviewed-by: Ronald G. Minnich 
    Tested-by: Ronald G. Minnich 
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    (cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084)

exynos5420: enable DMC internal clock gating

lets enable memory controller internal clock gating for ddr3.
    with these bits enabled we save some power out of ddr3.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60774

Signed-off-by: David Hendricks

Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
    Reviewed-on: https://gerrit.chromium.org/gerrit/65728
    Reviewed-by: Ronald G. Minnich 
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    (cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781)

exynos5420: Correct the 600MHz PMS value

In UM ver0.02, 600MHz clock PMS values differs from what is programed
    currently. Though this also results in 600MHz clock, but it is better to
    match what UM says. This patch chnage this as per UM

This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3
    (Note: we already used the correct 600MHz value for KPLL)

Signed-off-by: David Hendricks

Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5
    Reviewed-on: https://gerrit.chromium.org/gerrit/65726
    Reviewed-by: Ronald G. Minnich 
    Tested-by: Ronald G. Minnich 
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    (cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f)

Squashed five commits pertaining to  exynos.

Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992
    Signed-off-by: Isaac Christensen 
    Reviewed-on: http://review.coreboot.org/6425
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan

See http://review.coreboot.org/6425 for details.

-gerrit