Ethan Tsao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58317 )
Change subject: soc/intel/common/acpi: Correct IPC sub command for reading LPM requirement ......................................................................
soc/intel/common/acpi: Correct IPC sub command for reading LPM requirement
Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC.
Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765 Signed-off-by: Ethan Tsao ethan.tsao@intel.com --- M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58317/1
diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index fe38a36..8f6fcbf 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -47,7 +47,8 @@ const uint32_t offset = lpm->lpm_ipc_offset + i * lpm->req_reg_stride + j * sizeof(uint32_t); - const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_RD_PMC_REG, 0, 0); + const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_RD_PMC_REG, + PMC_IPC_CMD_SUBCMD_RD_PMC_REG, 0); struct pmc_ipc_buffer req = {.buf[0] = offset}; struct pmc_ipc_buffer res = {};
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index 1877fe4..c42a563 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -39,7 +39,8 @@ #define PMC_IPC_CMD_NO_MSI 0
/* IPC command for reading PMC registers */ -#define PMC_IPC_CMD_RD_PMC_REG 0xA0 +#define PMC_IPC_CMD_RD_PMC_REG 0xA0 +#define PMC_IPC_CMD_SUBCMD_RD_PMC_REG 0x02
/* IPC command to enable/disable PCIe SRCCLK */ #define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC