[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 36:

(1 comment)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/dc4f9586_ae1c166d?usp... :
PS30, Line 141: 0xfe02c000
> Hi Subrata, understood your point here, for PTL as per, we initally are using "[PchSerialIoIndexUART0] = PchSerialIoPci," config, but we will revert to use "PchSerialIoSkipInit". 
> Once FSP is externally released, we can come back and share the obersvation of usin g CONSOLE_UART_BASE_ADDRESS value independent of FSP settings.

Please create a BUG with FIXME tag so, we know that we need to clean this code. Post that, mark this comment resolved.