[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email )

Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................

Patch Set 5:

(6 comments)

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/84103/comment/64ef8a3f_23e44e2d?usp... :
PS5, Line 29: GPE1_STS
> sure. will make the change.

can you please use my git diff

```
git diff 
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 25854837faf..84b8467070b 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -26,9 +26,10 @@
 #define  CPUID_6_EAX_ISST      (1 << 7)

#define ACPI_SCI_IRQ 9
-#ifndef GPE1_STS
+#if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)
 /* NOTE: For platform doesn't have support for GPE1, adding dummy entry here for common code */
-#define  GPE1_STS(x)        (0x0 + ((x) * 4))
+#define GPE1_STS(x) (0x0 + ((x) * 4))
+#define GPE1_REG_MAX 0
 #endif

void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
@@ -112,7 +113,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
        fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);

fadt->gpe1_blk =  GPE1_STS(0) ? (pmbase + GPE1_STS(0)) :  GPE1_STS(0);
-       if (!fadt->gpe1_blk) {
+       if (fadt->gpe1_blk) {
                fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t);
                /*
                 * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets.
```

https://review.coreboot.org/c/coreboot/+/84103/comment/49b1c7a5_5e5b01c6?usp... :
PS5, Line 31:         
just use one space

https://review.coreboot.org/c/coreboot/+/84103/comment/b421e148_e0e364af?usp... :
PS5, Line 31:  
drop one space

https://review.coreboot.org/c/coreboot/+/84103/comment/27afe9c2_9d9fa368?usp... :
PS5, Line 114:  
one space

https://review.coreboot.org/c/coreboot/+/84103/comment/60cb67e7_fb23541d?usp... :
PS5, Line 115: !fadt->gpe1_blk
we wish to program gpe1_blk_len if gpe1_blk is not zero.
```
    if (fadt->gpe1_blk) {
```

https://review.coreboot.org/c/coreboot/+/84103/comment/fd793e7f_bd04a900?usp... :
PS5, Line 116: GPE1_REG_MAX
not defined