Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80702?usp=email )
Change subject: vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum name ......................................................................
vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum name
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702 Reviewed-by: Elyes Haouas ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 2ef3e8b..64a8b3e 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -43,7 +43,7 @@ };
/* Sync with PCIE_ASPM_TYPE */ -enum pcie_asmp { +enum pcie_aspm { aspm_disabled, L0s, L1, @@ -57,7 +57,7 @@ uint8_t gpio_group; enum mpio_hotplug hotplug; enum pcie_link_speed speed; - enum pcie_asmp aspm; + enum pcie_aspm aspm; uint8_t aspm_l1_1 : 1; uint8_t aspm_l1_2 : 1; uint8_t clock_pm : 1;