Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt
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Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48947/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/48947/2//COMMIT_MSG@9
PS2, Line 9: can has
*can have* or just *has*
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6
Gerrit-Change-Number: 48947
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Gerrit-Comment-Date: Mon, 28 Dec 2020 09:57:09 +0000
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