Attention is currently required from: Werner Zeh.
Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69387 )
Change subject: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver ......................................................................
mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed.
This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link
TEST=Try different register values to verify LED feature.
Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 51 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69387/1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig index 00875fb..a3aba3a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig @@ -6,6 +6,7 @@ select DRIVER_INTEL_I210 select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE select EHL_TSN_DRIVER + select DRIVERS_PHY_M88E1512
config FMDFILE default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4109ec9..492122a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -161,12 +161,39 @@ device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE) - device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 - device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 + # Enable external Marvell PHY 88E1512 + chip drivers/phy/m88e1512 + register "led_customize" = "1" + # LED[0]: On - 1000 Mbps Link, Off - Else + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_ctrl" = "0x17" + device pnp 0.0 on end # PHY address + end + end + device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1 + # Enable external Marvell PHY 88E1512 + chip drivers/phy/m88e1512 + register "led_customize" = "1" + # LED[0]: On - 1000 Mbps Link, Off - Else + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_ctrl" = "0x17" + device pnp 0.1 on end # PHY address + end + end
device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.4 on end # PCH Time-Sensitive Networking GbE + device pci 1e.4 on # PCH Time-Sensitive Networking GbE + # Enable external Marvell PHY 88E1512 + chip drivers/phy/m88e1512 + register "led_customize" = "1" + # LED[0]: On - 1000 Mbps Link, Off - Else + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_ctrl" = "0x17" + device pnp 1.1 on end # PHY address + end + end
device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm