[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85569?usp=email )

Change subject: soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE
......................................................................

soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE

Make use of exception handling in every stage. Additionally this
enables breakpoints in all stages, making NULL dereferences and
stack overflows easier to detect.

TEST: Stack canary exceptions are seen in romstage on ibm/sbp1.

Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/85569/1

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index e1a4ac5..f61de56 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -46,6 +46,7 @@
    select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
    select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
    select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	select IDT_IN_EVERY_STAGE

if XEON_SP_COMMON_BASE